The present invention relates to a semiconductor device and a semiconductor device measuring method and, more particularly, relates to a test element group (TEG) for testing a semiconductor device.
TEGs are used to secure the reliability of semiconductor devices such as semiconductor integrated circuits. For a semiconductor device, the manufacturing process, circuit characteristics and device reliability are evaluated by characteristic evaluation made using TEGs. When a semiconductor device is in a manufacturing stage, the device reliability is evaluated based on the results of measurement made using TEGs. Based on the evaluation results, the device manufacturing process or circuit design is modified. In the case of a finished semiconductor device, the device reliability is evaluated and whether the device is faultless is determined.
Generally, TEGs for electric characteristics control are provided in scribe regions formed over semiconductor wafers. The scribe regions include scribe lines formed to isolate individual semiconductor chips. In recent years, with semiconductor circuits being formed in higher integration density and with the types of transistors used and the number of wiring layers included in semiconductor circuits tending to increase, the number of device evaluation items to be managed has been increasing. As a result, the numbers of testing elements included in TEGs have also been increasing. Under such circumstances, various TEG configurations and measuring methods using TEGs have been proposed.
For example, Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2004-537859 discloses a technique used to design a testing configuration in which a test is performed to determine whether a via-hole or contact included in a via-hole or contact chain has an abnormally high resistance. Japanese Unexamined Patent Application Publication No. 2005-203578 discloses a technique aimed at evaluating, with high sensitivity, contacts or via-holes in a large scale and in a short period of time. In Japanese Unexamined Patent Application Publication No. 2002-110753, a technique is disclosed according to which, corresponding to the contacts included in an IC, as many contacts for evaluation as possible are formed and the contacts for evaluation are individually evaluated to enable highly reliable contact characteristic evaluation.